Abstracto

Performance improvement in FIR filter using Residue Number System with modulo adders and multipliers

Mythili.M, Gowrishankar.V, Venkatachalam.K.V

Digital Signal Processing (DSP) systems are the core of wide range of applications like audio, video, image processing and consumer electronics.Most of the DSPs involve repetitive operations of addition, subtraction and multiplication on large integers.A digital Finite Impulse Response (FIR) filter performs the frequency shaping or linear prediction on a discrete-time input sequence {x0, x1, x2….}. In this work we focused on the design of an efficient VLSI (Very Large Scale integration) architecture for FIR filters which aims at reducing the power consumption, increasing the speed and also to reduce the hardware complexity using Residue Number System (RNS). This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in RNS domain. It uses modulo adders and modulo multipliers to obtain high speed performance.