Abstracto

Network Data Security Using FPGA

Ms.P.Thamarai , Mr.B.Karthik

This paper approaches a new and simple technique to develop the RSA algorithm using FPGA that can be used as a standard device in the secured communication system. This RSA algorithm is implemented in the FPGA with the help of VHDL. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This results in very low frequency requirement to perform this operation with consideration of high speed by reducing the gate counts with low power consumption of whole circuit, multiple key size support and low cost compared to earlier methods. The information to RSA encryption side is in the form of statement and the same will appear in the decryption side and its real time input/output also achieved effectively. The hardware design is targeted on Xilinx Spartan 3E device and it supports lower versions as well. The RSA algorithm design has made use of 951 total equivalent gate counts and achieved a clock frequency of 35.00MHz.