Abstracto

HDLC Protocol Implementation Using VHDL

Sarika G. Joshi , Vaishali S. Dhongde, Prof. Mrs.Mansi Wargantwar

To successfully transmit data over any network, a protocol is required to manage the flow or space at which the data is transmitted. High-level Data Link Control HDLC is a group of protocols for transmitting synchronous data packets between point-to- point nodes. In HDLC, data is organized into a frame. It resides on Layer 2 of the Open System Interconnect model, i.e. data link layer. HDLC uses zero insertion/deletion process called bit stuffing to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags. The HDLC frame is synchronous and therefore realizes on the physical layer to provide method of clocking and synchronizing the transmission and reception of frames. It is the most commonly used Layer 2 protocol and is suitable for bit oriented packet transmission mode.[1,2]The project analyses the methods of HDLC procedure implementation commonly used nowadays, & point out their defects. These HDLC procedures are based on Field Programmable Gates Array (FPGA) & specially illustrate how to generate Frame Check Sequence i.e. Cyclic redundancy Check of HDLC in FPGA.These methods are verified by downloading the HDLC modules designed in VHDL into Xilinx9.1 ISE,on FPGA Spartan3 IM Protoboard model - MXS3FK-IM as a target technology, which shows the feasibility of the methods. The programming modules are simple, easy to modify, & superior in practical application. To make the project user friendly a graphical user interface (GUI) is designed in Visual C ++. Which allows the character byte to enter through keyboard and also shows an output data received through GUI