Abstracto

Design and Verification of High Speed SDRAM Controller with Adaptive Bank Management and Command Pipeline

Ganesh Mottee, P.Shalini

As the performance gap between microprocessors and memory continues to increase,main memory accesses result in long latencies which become a factor limiting system performance. Previous studies show that main memory access streams contain significant Localities and SDRAM devices provide parallelism through multiple banks and channels.These locality and parallelism have not been exploited thoroughly by conventional memory controllers. In this thesis, SDRAM address mapping techniques and memory access reordering mechanisms are studied and applied to memory controller design with the goal of reducing observed main memory access latency. The application of the synchronous dynamic random access memory (SDRAM) has gone beyond the scope of personal computers for quite a long time. It comes into hand whenever a big amount of low price and still high speed memory is needed. Most of the newly developed stand alone embedded devices in the field of image, video and sound processing take more and more use of it. The big amount of low price memory has its trade off – the speed. In order to take use of the full potential of the memory, an efficient controller is needed. Efficient stands for maximum random accesses to the memory both for reading and writing and less area after implementation.